Reference is made to FIG. 1 which illustrates a circuit diagram for a prior art hysteresis comparator circuit 10 (known to those skilled in the art as an Alstott comparator; Alstott “A precision variable supply CMOS comparator,” IEEE Journal of Solid State Circuits, vol. 17, no. 6 (December 1982), the disclosure of which is incorporated by reference). The circuit 10 includes a MOSFET transistor 12 configured to operate as a tail current source for a differential input circuit 14 formed by MOSFET transistors 16 and 18. The transistors 12, 16 and 18 are n-channel devices. The source terminal of transistor 12 is coupled to a ground reference node and the drain terminal of transistor 12 is coupled to a common node 20. The gate terminal of transistor 12 is coupled to receive a bias voltage (BIAS). The source terminals of transistors 16 and 18 are coupled to the common node 20 and the drain terminals of transistors 16 and 18 are coupled to intermediate nodes 22 and 24, respectively. The gate terminal of transistor 16 forms the non-inverting input (INP) of the comparator circuit 10 and the gate terminal of transistor 16 forms the inverting input (INN) of the comparator circuit 10. The output (OUTN or OUTP) of the differential input circuit 14 may be taken at either node 22 or node 24. The outputs OUTP and OUTN are differential analog signals. These analog output signals are converted to a digital output (DATAOUT) by a differential to single-ended converter circuit 40 as known to those skilled in the art.
The load circuit 26 of the differential input circuit 14 is formed by a plurality of p-channel MOSFET devices. A pair of cross-coupled transistors 28 and 30 is coupled between the differential input circuit 14 and a positive supply node (Vdd). The transistor 28 has a source-drain path coupled in series with the source-drain path of the transistor 16. In this configuration, the source terminal of transistor 28 is coupled to the positive supply node and the drain terminal of transistor 28 is coupled to the intermediate node 22 (and drain terminal of transistor 16). The gate terminal of transistor 28 is coupled to the intermediate node 24 (and drain terminal of transistor 18). The transistor 30 has a source-drain path coupled in series with the source-drain path of the transistor 18. In this configuration, the source terminal of transistor 30 is coupled to the positive supply node and the drain terminal of transistor 30 is coupled to the intermediate node 24 (and drain terminal of transistor 18). The gate terminal of transistor 30 is coupled to the intermediate node 22 (and drain terminal of transistor 16). A first diode-connected transistor 32 is coupled in parallel with the transistor 28. Thus, the source terminal of transistor 32 is coupled to the positive supply node and the drain terminal of transistor 32 is coupled both to the gate terminal of transistor 32 and the intermediate node 22. A second diode-connected transistor 34 is coupled in parallel with the transistor 30. Thus, the source terminal of transistor 34 is coupled to the positive supply node and the drain terminal of transistor 34 is coupled both to the gate terminal of transistor 34 and the intermediate node 24.
The transistors 28 and 30 contribute positive feedback providing additional paths for charging the intermediate nodes 22 and 24. This feedback shifts the switching point of the comparator. The size of the transistors 32 and 34 affects the triggering voltage of the comparator. The comparator circuit 10 accordingly operates with a hysteresis value which is determined by the ratio of the β for transistors 28 or 30 to the β for transistors 32 or 34. However, it in noted that this hysteresis value is vulnerable to process and temperature variation. There is accordingly a need in the art for a comparator circuit having a controllable and stable hysteresis value.